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order number: mpc107ec/d rev. 0.5, 4/2001 semiconductor products sector this document contains information on a new product under development by motorola. motorola reserves the right to change or discontinue this product without notice. ? motorola, inc., 2001. all rights reserved. advance information mpc107 bridge/memory controller hardware speci?ations this document provides an overview of the mpc107 pci bridge/memory controller (pcib/mc) for high-performance embedded systems. the mpc107 is a cost-effective, general-purpose pci bridge/memory controller for applications using pci in networking infrastructure, telecommunications, and other embedded markets. it can be used in applications such as network routers and switches, mass storage subsystems, network appliances, and print and imaging systems. this document describes pertinent electrical and physical characteristics of the mpc107. for functional characteristics of the processor, refer to the mpc107 risc bridge/memory controller users manual (mpc107um/d). this document contains the following topics: topic page section 1.1, ?overview? 2 section 1.2, ?features? 3 section 1.3, ?general parameters? 4 section 1.4, ?electrical and thermal characteristics? 5 section 1.5, ?package description? 27 section 1.6, ?pll con guration? 34 section 1.7, ?system design information? 35 section 1.8, ?document revision history? 40 section 1.9, ?ordering information? 43
2 mpc107 bridge/memory controller hardware speci?ations overview to locate any published errata or updates for this document, refer to the web site at http://www.motorola.com/semiconductors. 1.1 overview the mpc107 integrates a pci bridge, memory controller, dma controller, epic interrupt controller/timers, a message unit with an intelligent input/output (i 2 o) message controller, and an inter-integrated circuit (i 2 c) controller. the integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. figure 1 shows the major functional units within the mpc107. note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented. figure 1. mpc107 block diagram 60x bus interface (64- or 32-bit data bus) address translator dll fanout buffers pci arbiter message unit (with i 2 o) i 2 c controller dma controller interrupt controller epic /timers pci bus interface unit memory controller data path ecc controller central control unit 32-bit osc_in five request/grant pairs i 2 c 5 direct/ peripheral logic block pll pci bus data (64-bit) address data bus (64- or 32-bit) memory/rom/ port x control/ pci interface clocks 16 serial interrupts configuration registers (32-bit) with 8-bit parity or ecc mpc107 pci_sync_in address sdram clocks cpu clocks sdram_sync_in additional features: programmable i/o with watchpoint jtag/cop interface power management
mpc107 bridge/memory controller hardware speci?ations 3 features 1.2 features the mpc107 provides an integrated high-bandwidth, high-performance interface between up to two 60x processors, the pci bus, and main memory. this section summarizes the major features of the mpc107, as follows: memory interface ? 64-/32-bit 100-mhz bus ? programmable timing supporting either fpm dram, edo dram, or sdram ? high-bandwidth bus (32-/64-bit data bus) to dram ? supports one to eight banks of 4-, 16-, 64-, or 128-mbit memory devices, and up to four banks of 256-mbit sdram devices ? supports 1-mbyte to 1-gbyte dram memory ? 144 mbytes of rom space ? 8-, 32-, or 64-bit rom ? write buffering for pci and processor accesses ? supports normal parity, read-modify-write (rmw), or ecc ? data-path buffering between memory interface and processor ? low-voltage ttl logic (lvttl) interfaces ? port x: 8-, 32-, or 64-bit general-purpose i/o port using rom controller interface with programmable address strobe timing 32-bit pci interface operating up to 66 mhz ? pci 2.1-compliant ? pci 5.0-v tolerance ? support for pci locked accesses to memory ? support for accesses to pci memory, i/o, and con guration spaces ? selectable big- or little-endian operation ? store gathering of processor-to-pci write and pci-to-memory write accesses ? memory prefetching of pci read accesses ? selectable hardware-enforced coherency ? pci bus arbitration unit ( ve request/grant pairs) ? pci agent mode capability ? address translation unit ? some internal con guration registers accessible from pci two-channel integrated dma controller (writes to rom/port x not supported) ? supports direct mode or chaining mode (automatic linking of dma transfers) ? supports scatter gathering?read or write discontinuous memory ? interrupt on completed segment, chain, and error ? local-to-local memory ? pci-to-pci memory ? pci-to-local memory ? pci memory-to-local memory
4 mpc107 bridge/memory controller hardware speci?ations general parameters message unit ? two doorbell registers ? an extended doorbell register mechanism that facilitates interprocessor communication through interrupts in a dual-local-processor system ? two inbound and two outbound messaging registers ?i 2 o message controller i 2 c controller with full master/slave support (except broadcast all) embedded programmable interrupt controller (epic) ? five hardware interrupts (irqs) or 16 serial interrupts ? four programmable timers integrated pci bus, cpu, and sdram clock generation programmable pci bus, 60x, and memory interface output drivers dynamic power management supporting 60x nap, doze, and sleep modes programmable input and output signals with watchpoint capability built-in pci bus performance monitor facility debug features ? error injection/capture on data path ? ieee 1149.1 (jtag)/test interface processor interface ? supports up to two powerpc? microprocessors with 60x bus interface ? supports various operating frequencies and bus divider ratios ? 32-bit address bus, 64/32-bit data bus supported at 100 mhz ? supports full memory coherency ? supports optional local bus slave ? decoupled address and data buses for pipelining of 60x accesses ? store gathering on 60x-to-pci writes ? concurrent transactions on 60x and pci buses supported 1.3 general parameters the following list provides a summary of the general parameters of the mpc107: technology: 0.29 m cmos, ve-layer metal die size: 50 mm 2 transistor count: 0.96 million logic design: fully static package: surface mount 503 plastic ball grid array (c4/pbga) core power supply: 2.5v 5% v dc (nominal; see table 2 for recommended operating conditions) i/o power supply: 3.0 to 3.6 v dc
mpc107 bridge/memory controller hardware speci?ations 5 electrical and thermal characteristics 1.4 electrical and thermal characteristics this section provides the ac and dc electrical speci cations and thermal characteristics for the mpc107. 1.4.1 dc electrical characteristics 1.4.1.1 absolute maximum ratings the tables in this section describe the mpc107 dc electrical characteristics. table 1 provides the absolute maximum ratings. 1.4.1.2 recommended operating conditions table 2 provides the recommended operating conditions for the mpc107. table 1. absolute maximum ratings characteristic 1 symbol range unit supply voltage - core vdd -0.3 to 2.75 v supply voltage - memory bus drivers gvdd -0.3 to 3.6 v supply voltage - processor bus drivers bvdd -0.3 to 3.6 v supply voltage - pci and standard i/o buffers ovdd -0.3 to 3.6 v supply voltage - plls and dll avdd/lavdd -0.3 to 2.75 v supply voltage - pci reference lvdd -0.3 to 5.4 v input voltage 2 v in -0.3 to 3.6 v operational die-junction temperature range t j 0 to 105 c storage temperature range t stg -55 to 150 c notes: 1. functional and tested operating conditions are given in table 2 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. pci inputs with lvdd = 5v 5% v dc may be correspondingly stressed at voltages exceeding lvdd + 0.5 v dc. table 2. recommended operating conditions 1 characteristic symbol recommended value unit notes supply voltage vdd 2.5 5% v 5 supply voltages for memory bus drivers gvdd 3.3 5% v 7 supply voltages for processor bus drivers bvdd 3.3 5% v7 2.5 5% i/o buffer supply for pci and standard ovdd 3.3 0.3 v 5 pll supply voltage avdd 2.5 5% v 6 dll supply voltage lavdd 2.5 5% v 6
6 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics pci reference lvdd 5.0 5% v 8,9 3.3 0.3 v 8,9 input voltage pci inputs v in 0 to 3.6 or 5.75 v 2,3 all other inputs 0 to 3.6 v 4 die-junction temperature t j 0 to 105 c notes: 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. pci pins are designed to withstand lvdd + 0.5 v dc when lvdd is connected to a 5.0v dc power supply. 3. pci pins are designed to withstand lvdd + 0.5 v dc when lvdd is connected to a 3.3 v dc power supply. cautions: 4. input voltage (v in ) must not be greater than the supply voltage (vdd/avdd/lavdd) by more than 2.5 v at all times including during power-on reset. 5. ovdd must not exceed vdd/avdd/lavdd by more than 1.8 v at any time including during power-on reset. 6. vdd/avdd/lavdd must not exceed ovdd by more than 0.6 v at any time including during power-on reset. 7. bvdd/gvdd must not exceed vdd/avdd/lavdd by more than 1.8 v at any time including during power-on reset. 8. lvdd must not exceed vdd/avdd/lavdd by more than 5.4 v at any time including during power-on reset. 9. lvdd must not exceed ovdd by more than 3.6 v at any time including during power-on reset. table 2. recommended operating conditions (continued) 1 characteristic symbol recommended value unit notes
mpc107 bridge/memory controller hardware speci?ations 7 electrical and thermal characteristics figure 2 shows supply voltage sequencing and separation cautions. figure 2. supply voltage sequencing and separation cautions ovdd/bvdd/gvdd/(lvdd@3.3v - - - -) vdd/avdd/lavdd lvdd@5v time 3.3v 5v 2.5v 0 6 9 8 8 9 5,7 dc power supply voltage voltage regulator delay 2 reset configuration pins hreset pll relock time 3 100 s 9 external memory asserted 255 external memory hreset vdd stable power supply ramp up 2 see note 1 below. clock cycles 3 clock cycles setup time 4 vm = 1.4 v notes: 1. numbers associated with waveform separations correspond to caution numbers listed in table 2. 2. refer to section 1.7.2, ?power supply voltage sequencing,? for additional information on this topic. 3. refer to table 8 for additional information on pll relock and reset signal assertion timing requirements. 4. refer to table 9. for additional information on reset con guration pin setup timing requirements. 5. hreset must transition from a logic 0 to a logic 1 in less than one sdram_sync_in clock cycle for the device to be in the non-reset state. 6. hreset_cpu negates 2 17 memory clock cycles after hreset negates. hreset_cpu vm = 1.4 v maximum rise time must be less than one external memory clock cycle 5 6
8 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics figure 3 shows the undershoot and overshoot voltage of the memory interface of the mpc107. figure 3. overshoot/undershoot voltage 1.4.1.3 dc electrical characteristics table 3 provides the dc electrical characteristics for the mpc107. table 3. dc electrical specifications at recommended operating conditions (see table 2 ) characteristics conditions 4 symbols min max units input high voltage 6 pci only v ih 0.65*ovdd lvdd v input low voltage pci only v il ? 0.3*ovdd v input high voltage all other pins (gvdd = 3.3v) v ih 2.0 ? v input high voltage all other pins (bvdd = 2.5v) v ih 1.7 ? v input low voltage all inputs except pci_sync_in v il gnd 0.8 v pci_sync_in input high voltage cv ih 2.4 ? v pci_sync_in input low voltage cv il gnd 0.4 v input leakage current 5 for pins using drv_pci driver. 0.5 v v in 2.7 v @ lvdd = 4.75 i l ? 70 a input leakage current 5 all others lvdd = 3.6 v (gvdd 3.465) i l ? 10 a output high voltage i oh =driver dependent 3 (gvdd = 3.3v) v oh 2.4 ? v output low voltage i ol =driver dependent 3 (gvdd = 3.3v) v ol ? 0.4 v output high voltage i oh =driver dependent 3 (bvdd = 2.5v) all outputs except cpuclks[0?2] v oh 1.85 ? v i oh =driver dependent 3 (bvdd = 2.5v) cpuclks[0?2] only v oh 2.0 ? v gnd gnd - 0.3v gnd - 1.0v not to exceed 10% gvdd of t sdram_clk gvdd + 5% 4 v v ih v il
mpc107 bridge/memory controller hardware speci?ations 9 electrical and thermal characteristics notes: 1. see figure 17 for pins with internal pull-up resistors. 2. capacitance is periodically sampled rather than 100% tested. 3. see table 4 for the typical drive capability of a speci c signal pin based upon the type of output driver associated with that pin as listed in table 17. 4. these speci cations are for the default driver strengths indicated in table 4. 5. leakage current is measured on input pins and on output pins in the high impedance state. the leakage current is measured for nominal ovdd/lvdd and vdd or both ovdd/lvdd and vdd must vary in the same direction. 6. the minimum input high voltage is not compliant with the pci local bus speci cation (rev 2.1) which speci es 0.5*ovdd for minimum input high voltage. 1.4.1.4 output driver characteristics table 4 provides information on the characteristics of the output drivers referenced in table 17. the values are from the mpc107 ibis model (v1.1) and are not tested. for additional detailed information, see the complete ibis model listing at http://www.motorola.com/semiconductors. output low voltage i ol =driver dependent 3 (bvdd = 2.5v) all outputs except cpuclks[0?2] v ol ? 0.4 v i ol =driver dependent 3 (bvdd = 2.5v) cpuclks[0?2] only v ol ? 0.3 v capacitance 2 v in =0 v, f=1mhz c in ? 7.0 pf table 4. drive capability of mpc107 output pins driver type programmable output impedance (ohms) supply voltage i oh i ol units notes drv_cpu 20 bvdd = 3.3v 36.6 18.1 ma 2, 5 bvdd = 2.5v 21.4 15.6 ma 3, 6, 7 40 (default) bvdd = 3.3v 18.6 9.2 ma 2, 5 bvdd = 2.5v 10.8 7.9 ma 3, 6, 7 drv_pci 25 ovdd = 3.3 12.0 12.4 ma 1, 4 50 (default) ovdd = 3.3 6.1 6.3 ma 1, 4 drv_mem_addr drv_pci_clk 8 (default) gvdd = 3.3 89.0 42.3 ma 2, 5 13.3 gvdd = 3.3 55.8 26.4 ma 2, 5 20 gvdd = 3.3 36.6 18.1 ma 2, 5 40 gvdd = 3.3 18.6 9.2 ma 2, 5 drv_mem_data 20 (default) gvdd = 3.3 36.6 18.1 ma 2, 5 40 gvdd = 3.3 18.6 9.2 ma 2, 5 table 3. dc electrical specifications (continued) at recommended operating conditions (see table 2 )
10 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics notes: 1.for drv_pci, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.33v label by interpolating between the 0.3 v and 0.4 v table entries? current values which corresponds to the pci v oh = 2.97 = 0.9*ovdd (ovdd = 3.3 v) where table entry voltage = ovdd - pci v oh . 2. for all others with gvdd or bvdd = 3.3 v, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.9 v table entry which corresponds to the v oh = 2.4 v where table entry voltage = g/bvdd - v oh . 3.for all others with bvdd = 2.5 v, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.65 v table entry by interpolating between the 0.6 v and 0.7 v table entries? current values which corresponds to the v oh = 1.85 v where table entry voltage = bvdd - v oh . 4. for drv_pci, i ol read from the ibis listing in the pull-down mode, i(min) column, at 0.33 v = pci v ol = 0.1*ovdd (ovdd = 3.3 v) by interpolating between the 0.3 v and 0.4 v table entries. 5. for all others with gvdd or bvdd = 3.3 v, i ol read from the ibis listing in the pull-down mode, i(min) column, at the 0.4 v table entry. 6.for all others with bvdd = 2.5 v, i ol read from the ibis listing in the pull-down mode, i(min) column, at the 0.4 v table entry. 7.for bvdd = 2.5 v, the i oh and i ol values are estimated from the io_mem_data_xx_2.5 and io_mem_addr_xx_2.5 sections of the ibis model where xx = driver output impedance (20 or 40 ohms). 1.4.1.5 power characteristics table 5 provides the preliminary power consumption estimates for the mpc107. table 5. power consumption mode pci_sync_in/core frequency (mhz) units notes 25/50 33/33 33/66 66/100 vdd pwr i/o pwr vdd pwr i/o pwr vdd pwr i/o pwr vdd pwr i/o pwr maximum tbd tbd tbd tbd tbd tbd tbd tbd mw typical 400 1125 300 925 550 1325 800 1375 mw 1,2 doze 375 850 250 775 500 975 750 1125 mw 1,2 nap 375 875 250 825 500 1025 750 1150 mw 1,2 sleep 175 875 125 825 225 1025 325 1150 mw 1,2 sleep 125 725 100 650 175 875 275 1025 mw 1,2,3 sleep 125 575 100 500 175 650 250 675 mw 1,3,4 sleep 10 400 10 425 10 425 25 500 mw 1,3,4,5 reset 550 850 350 675 700 975 1050 950 mw 1,2 notes: 1. power is measured with vdd = 2.625v, gvdd = ovdd = bvdd = 3.45 v at 0 c and one dimm populated in test system. 2. all clock drivers enabled. 3. memory refresh off. 4. one pci_clk, one cpu_clk, and one sdram_clk enabled. 5. pll off. 6. power consumption on the pll supply pin (avdd) and the dll supply pin (lavdd) < 15 mw. this parameter is guaranteed by design and is not tested.
mpc107 bridge/memory controller hardware speci?ations 11 electrical and thermal characteristics 1.4.2 thermal characteristics table 6 provides the package thermal characteristics for the mpc107. 1.4.3 ac electrical characteristics this section provides the ac electrical characteristics for the mpc107. after fabrication, functional parts are sorted by maximum core frequency as shown in table 7 and section 1.4.3.1, ?clock ac speci cations,? and tested for conformance to the ac speci cations for that frequency. the core frequency is determined by the bus (pci_sync_in) clock frequency and the settings of the pll_cfg[0?3] signals. parts are sold by maximum processor core frequency; see section 1.9, ?ordering information.? table 7 provides the operating frequency information for the mpc107. 1.4.3.1 clock ac speci?ations table 8 provides the clock ac timing speci cations as de ned in section 1.4.3.2. table 6. pbga package thermal characteristics characteristic 1 symbols value units die junction-to-case thermal resistance jc < 0.1 c/w die junction-to-board thermal resistance jb 5.2 c/w package junction-to-ambient thermal resistance 2 ja see figure 25 notes: 1. refer to section 1.7, ?system design information,? for more details about thermal management . 2. t j = t a + p d x ja t j = die junction temperature t a = system air ambient temperature near the package p d = average power consumed by ic in watts ja = thermal resistance from die junction to ambient air in c/w table 7. operating frequency at recommended operating conditions (see table 2 ) with lvdd = 3.3 v 0.3 v characteristic 1 66 mhz 100 mhz units min max min max core (memory bus/processor bus) frequency 25 66 25 100 mhz pci input frequency (pci_sync_in) 12.5?66 mhz notes: caution: the pci_sync_in frequency and pll_cfg[0?3] settings must be chosen such that the resulting peripheral logic/memory bus frequency, cpu (core) frequency, and pll (vco) frequencies do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0?3] signal description in section 1.6, ?pll con guration,? for valid pll_cfg[0?3] settings and pci_sync_in frequencies.
12 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics notes: 1 these speci cations are for the default driver strengths indicated in table 4. 2 rise and fall times for the pci_sync_in input are measured from 0.4 to 2.4 v. 3 speci cation value at maximum frequency of operation. 4 relock time is guaranteed by design and characterization. relock time is not tested. 5 rise and fall times for the osc_in input are guaranteed by design and characterization. osc_in input rise and fall times are not tested. 6 relock timing is guaranteed by design. pll-relock time is the maximum amount of time required for pll lock after a stable vdd and pci_sync_in are reached during the reset sequence. this speci cation also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the reset sequence. 7 dll_extend is bit 7 of the pmc2 register <72>. n is a non-zero integer (1 or 2). t clk is the period of one sdram_sync_out clock cycle in ns. t loop is the propagation delay of the dll synchronization feedback loop (pc board runner) from sdram_sync_out to sdram_sync_in in ns; 6.25 inches of loop length (unloaded pc board runner) corresponds to approximately 1 ns of delay. t x0 is a xed delay inherent in the design when the dll is at tap point 0 and the dll is contributing no delay; t x0 equals approximately 3 ns. see figure 6 for dll locking ranges. 8 see table 18 for pci_sync_in input frequency range for speci c pll_cfg[0?3] settings. table 8. clock ac timing specifications at recommended operating conditions (see table 2. ) with lvdd = 3.3 v 0.3 v num characteristics and conditions 1 min max unit notes 1a frequency of operation (pci_sync_in) 12.5 66 mhz 8 1b pci_sync_in cycle time 80 15 ns 8 2,3 pci_sync_in rise and fall times ? 2.0 ns 2 4 pci_sync_in duty cycle measured at 1.4 v 40 60 % 5a pci_sync_in pulse width high measured at 1.4v 6 9 ns 3 5b pci_sync_in pulse width low measured at 1.4v 6 9 ns 3 7 pci_sync_in jitter ? <150 ps 9a pci_clk[0?4] skew (pin to pin) ? 500 ps 9b sdram_clk[0?3] skew (pin to pin) ? 350 ps 9c cpu_clk[0?2] skew (pin to pin) ? 350 ps 9d sdram_clk[0?3]/cpu_clk[0?2] jitter ? 150 ps 10 internal pll relock time ? 100 s 3,4,6 15 dll lock range with dll_extend = 0 disabled 0 (nt clk - t loop - t x0 ) 7ns 7 16 dll lock range with dll_extend = 1 enabled (default) 0 (nt clk - t clk /2 - t loop - t x0 ) 7 ns 7 17 frequency of operation (osc_in) 12.5 66 mhz 8 18 osc_in cycle time 80 15 ns 8 19 osc_in rise and fall times ? 5 ns 5 20 osc_in duty cycle measured at 1.4 v 40 60 % 21 osc_in frequency stability ? 100 ppm
mpc107 bridge/memory controller hardware speci?ations 13 electrical and thermal characteristics figure 4 shows pci_sync_in input clock timing, figure 5 illustrates how the table 8 clock speci cations relate to the mpc107 clocking, and figure 6 shows the dll locking range loop delay versus frequency of operation. . figure 4. pci_sync_in input clock timing diagram figure 5. clock subsystem block diagram 5a 5b vm vm = midpoint voltage (1.4v) 2 3 cvil cvih 1 pci_sync_in vm vm dll pll core logic sys_logic_clk pci_clk[0:4] pci_sync_out pci_sync_in sdram_clk[0:3] sdram_sync_out sdram_sync_in osc_in cpu_clk[0:2] mpc107 specs. 9c,9d specs. 9b,9d specs. 1 - 7 spec. 9a specs. 17 - 23 spec. 10 specs. 15,16 note: specification numbers are from table 8.
14 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics figure 6. dll locking range loop delay vs. frequency of operation 1.4.3.2 input ac timing speci?ations table 9 provides the input ac timing speci cations. see figure 7 and figure 8. table 9. input ac timing specifications at recommended operating conditions (see table 2 ) with lvdd = 3.3 v 0.3 v num characteristic min max units notes 10a pci input signals valid to pci_sync_in (input setup) 3.0 ? ns 2,3 10b memory interface signals valid to sdram_sync_in (input setup) 2.0 ? ns 1,3 10c epic, misc. debug input signals valid to sdram_sync_in (input setup) 2.0 ? ns 1,3 10d i 2 c input signals valid to sdram_sync_in (input setup) 2.0 ? ns 1,3 10e mode select inputs valid to hreset (input setup) 9*t clk ? ns 1,3?5 10f 60x processor interface signals valid to sdram_sync_in (input setup) 2.0 ? ns 1,3 dll not guaranteed to lock n = 1 dll_extend = 1 n = 1 dll_extend = 0 n = 2 dll_extend = 1 dll will lock 0 ns t loop propagation delay time in nanoseconds t clk sdram_sync_out period and frequency 10 ns 5 ns 15 ns 100 mhz 10 ns 50 mhz 20 ns 33 mhz 30 ns 25 mhz 40 ns n = 2 dll_extend = 0
mpc107 bridge/memory controller hardware speci?ations 15 electrical and thermal characteristics notes: 1 all memory, processor, and related interface input signal speci cations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the v m = 1.4 v of the rising edge of the memory bus clock, sdram_sync_in. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the fre- quency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 7. 1 all pci signals are measured from ovdd/2 of the rising edge of pci_sync_in to 0.4*ovdd of the signal in question for 3.3 v pci signaling levels. see figure 8. 2 input timings are measured at the pin. 3t clk is the time of one sdram_sync_in clock cycle. 4 all mode select input signals speci cations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the v m = 1.4 v of the rising edge of the hreset signal. see figure 9. figure 7 shows input-output timing referenced to sdram_sync_in and figure 8 the input-output timing referenced to pci_sync_in . figure 7. input - output timing diagram referenced to sdram_sync_in 11a1 pci_sync_in (sdram_sync_in) to inputs invalid (input hold) 1.0 ? ns 2,3 11a2 memory interface signals sdram_sync_in to inputs invalid (input hold) 0.5 ? ns 1,3 11a3 60x processor interface signals sdram_sync_in to inputs invalid (input hold) 0 ? ns 1,3 11b hreset to mode select inputs invalid (input hold) 0 ? ns 1,3,5 table 9. input ac timing specifications (continued) at recommended operating conditions (see table 2 ) with lvdd = 3.3 v 0.3 v num characteristic min max units notes 11a vm vm = midpoint voltage (1.4v) memory 10b-d pci_sync_in inputs/outputs 13b 14b vm vm sdram_sync_in shown in 2:1 mode input timing output timing 12b-d 2.0 v 0.8 v 0.8 v 2.0 v
16 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics . figure 8. input - output timing diagram referenced to pci_sync_in figure 9 shows input timing for mode select signals. figure 9. input timing diagram for mode select signals 1.4.3.3 output ac timing speci?ation table 10 provides the processor bus ac timing speci cations for the mpc107. see figure 7 and figure 8. table 10. output ac timing specifications at recommended operating conditions (see table 2 ) with lvdd = 3.3 v 0.3 v num characteristic 3,6 min max units notes 12a pci_sync_in to output valid, 66 mhz pci, with sdma4 pulled-down to logic 0 state. see figure 11. ? 6.0 ns 2,4 pci_sync_in to output valid, 33 mhz pci, with sdma4 in the default logic 1 state. see figure 11. ? 11.0 ns 2,4 12b memory interface signals, sdram_sync_in to output valid ? 5.5 ns 1 12b1 memory interface signal: cke (100 mhz device), sdram_sync_in to output valid ? 5.5 ns 1 12b2 memory interface signal: cke (66 mhz device), sdram_sync_in to output valid ? 6.0 ns 1 12c epic, misc. debug signals, sdram_sync_in to ?alid ? 9.0 ns 1 12d i 2 c, sdram_sync_in to output valid ? 5.0 ns 1 ovdd2 10a 11a pci_sync_in pci 12a 13a 14a ovdd2 ovdd2 0.4*ovdd 0.615*ovdd 0.285*ovdd input timing output timing inputs/outputs vm vm = midpoint voltage (1.4v) 11b mode pins 10e hreset 2.0 v 0.8 v
mpc107 bridge/memory controller hardware speci?ations 17 electrical and thermal characteristics notes: 1 all memory and related interface output signal speci cations are speci ed from the v m = 1.4 v of the rising edge of the memory bus clock, sdram_sync_in to the ttl level (0.8 or 2.0 v) of the signal in question. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (proces- sor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 7. 2 all pci signals are measured from ovdd/2 of the rising edge of pci_sync_in to 0.285*ovdd or 0.615*ovdd of the signal in question for 3.3 v pci signaling levels. see figure 8. 3 all output timings assume a purely resistive 50 ohm load (see figure 10). output timings are measured at the pin; time-of- ight delays must be added for trace lengths, vias, and connectors in the system. 4 pci bussed signals are composed of the following signals: lock , ird y , c/be [0?3], par, trd y , frame , st op , devsel , perr , serr , ad[0?31], req [4?0], gnt [4?0], idsel , int a . 5 pci hold times can be varied; see section 1.4.3.3.1, ?pci signal output hold timing,? for information on pro- grammable pci output hold times. the values shown for item 13a are for pci compliance. 6 these speci cations are for the default driver strengths indicated in table 4. figure 10 shows the ac test load for the mpc107. figure 10. ac test load for the mpc107 1.4.3.3.1 pci signal output hold timing in order to meet minimum output hold speci cations relative to pci_sync_in for both 33 mhz and 66 mhz pci systems, the mpc107 has a programmable output hold delay for pci signals. the initial value of the output hold delay is determined by the values on the sdma4 and sdma3 reset con guration signals. further output hold delay values are available by programming the pci_hold_del value of the pmcr2 con guration register. table 11 describes the bit values for the pci_hold_del values in pmcr2. 12e 60x processor interface signals sdram_sync_in to output valid ? 5.5 ns 1 13a output hold, 66 mhz pci, with sdma4 and sdma3 pulled-down to logic 0 states. see table 11. 1.0 ? ns 2,4,5 output hold, 33 mhz pci, with sdma4 in the default logic 1 state and sdma3 pulled-down to logic 0 state. see table 11. 2.0 ? ns 2,4,5 13b output hold (for all others) 1 ? ns 1 14a pci_sync_in to output high impedance (t off for pci) ? 14.0 ns 2,4 14b sdram_sync_in to output high impedance (for all others) ? 4.0 ns 1 table 10. output ac timing specifications (continued) at recommended operating conditions (see table 2 ) with lvdd = 3.3 v 0.3 v num characteristic 3,6 min max units notes output z 0 = 50 ? ovdd/2 r l = 50 ? pin output measurements are made at the device pin.
18 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics . table 11. power management configuration register 2?x72 bit name reset value description 6?4 pci_hold_del xx0 pci output hold delay values relative to pci_sync_in. the initial values of bits 6 and 5 are determined by the reset con guration pins sdma4 and sdma3, respectively. as these two pins have internal pull-up resistors, the default value after reset is 0b110. while the minimum hold times are guaranteed at shown values, changes in the actual hold time can be made by incrementing or decrementing the value in these bit elds of this register via software or hardware con guration. the increment is in approximately 400 picosecond steps. lowering the value in the three bit eld decreases the amount of output hold available. 000 66 mhz pci. pull-down sdma4 con guration pin with a 2k ? or less value resistor. this setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as speci ed in figure 10 are met for a 66 mhz pci system. see figure 11 . 001 010 011 100 33 mhz pci. this setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as speci ed in figure 10 are met for a 33 mhz pci system. see figure 11 . 101 110 (default if reset con guration pins left unconnected) 111
mpc107 bridge/memory controller hardware speci?ations 19 electrical and thermal characteristics figure 11 shows the pci_hold_del affect on output valid and hold time. figure 11. pci_hold_del affect on output valid and hold time 1.4.3.4 i 2 c ac timing speci?ations table 12 provides the i 2 c input ac timing speci cations for the mpc107. pci_sync_in pci inputs/outputs ovdd2 ovdd2 33 mhz pci 12a, 8 ns for 33 mhz pci pci_hold_del = 100 12a, 6 ns for 66 mhz pci pci_hold_del = 000 13a, 2 ns for 33 mhz pci pci_hold_del = 100 13a, 1 ns for 66 mhz pci pci_hold_del = 000 output valid output hold diagram not to scale as pci_hold_del values decrease as pci_hold_del values increase pci inputs and outputs pci inputs/outputs 66 mhz pci
20 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics notes: 1 units for these speci cations are in sdram_clk/cpu_clk units. 2 the actual values depend on the setting of the digital lter frequency sampling rate (dffsr) bits in the fre- quency divider register i2cfdr. therefore, the noted timings in the above table are all relative to quali ed signals. the quali ed scl and sda are delayed signals from what is seen in real time on the i 2 c bus. the quali ed scl, sda signals are delayed by the sdram_clk/cpu_clk clock times dffsr times 2 plus 1 sdram_clk/cpu_clk clock. the resulting delay value is added to the value in the table (where this note is referenced). see figure 13. 3 timing is relative to the sampling clock (not scl). 4 fdr[n] refers to the frequency divider register i2cfdr bit n. 5 input clock low and high periods in combination with the fdr value in the frequency divider register (i2cfdr) determine the maximum i 2 c input frequency. see figure 13. table 13 provides the i 2 c frequency divider register (i2cfdr) information for the mpc107. table 12. i 2 c input ac timing specifications at recommended operating conditions (see figure 2 ) with lvdd = 3.3 v 0.3 v num characteristic min max unit notes 1 start condition hold time 4.0 ? clks 1,2 2 clock low period (the time before mpc107 will drive scl low as a transmitting slave after detecting scl low as driven by an external master.) 8.0 + (16 x 2 fdr[4:2] ) x (5 - 4({fdr[5],fdr[1]} == b?10) - 3({fdr[5],fdr[1]} == b?11) - 2({fdr[5],fdr[1]} == b?00) - 1({fdr[5],fdr[1]} == b?01)) ? clks 1,2,4, 5 3 scl/sda rise time (from 0.5v to 2.4v) ?1ms 4 data hold time 0 ? ns 2 5 scl/sda fall time (from 2.4 to 0.5v) ? 1 ms 6 clock high period (time needed to either receive a data bit or generate a start or stop.) 5.0 ? clks 1,2, 5 7 data setup time 3.0 ? ns 3 8 start condition setup time (for repeated start condition only) 4.0 ? clks 1,2 9 stop condition setup time 4.0 ? clks 1,2
mpc107 bridge/memory controller hardware speci?ations 21 electrical and thermal characteristics notes: 1 values are in khz unless otherwise speci ed. 2 fdr hex and divider (dec) values are listed in corresponding order. 3 multiple divider (dec) values will generate the same input frequency but each divider (dec) value will generate a unique output frequency as shown in table 14. table 13. mpc107 maximum i 2 c input frequency fdr hex 2 divider 2 (dec) max i 2 c input frequency 1 sdram_clk/c pu_clk @ 25 mhz sdram_clk/c pu_clk @ 33 mhz sdram_clk/c pu_clk @ 50 mhz sdram_clk/c pu_clk @ 100 mhz 20, 21 160, 192 862 1.13 mhz 1.72 mhz 3.44 mhz 22, 23, 24, 25 224, 256, 320, 384 555 733 1.11 mhz 2.22 mhz 0, 1 288, 320 409 540 819 1.63 mhz 2, 3, 26, 27, 28, 29 384, 448, 480, 512, 640, 768 324 428 649 1.29 mhz 4, 5 576, 640 229 302 458 917 6, 7, 2a, 2b, 2c, 2d 768, 896, 960, 1024, 1280, 1536 177 234 354 709 8, 9 1152, 1280 121 160 243 487 a, b, 2e, 2f, 30, 31 1536, 1792, 1920, 2048, 2560, 3072 92 122 185 371 c, d 2304, 2560 62 83 125 251 e, f, 32, 33, 34, 35 3072, 3584, 3840, 4096, 5120, 6144 47 62 95 190 10, 11 4608, 5120 32 42 64 128 12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192, 10240, 12288 24 31 48 96 14, 15 9216, 10240 16 21 32 64 16, 17, 3a, 3b, 3c, 3d 12288, 14336, 15360, 16384, 20480, 24576 12 16 24 48 18, 19 18432, 20480 8 10 16 32 1a, 1b, 3e, 3f 24576, 28672, 30720, 32768 6 8 12 24 1c, 1d 36864, 40960 4 5 8 16 1e, 1f 49152, 61440 3 4 6 12
22 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics table 14 provides the i 2 c output ac timing speci cations for the mpc107. notes: 1 units for these speci cations are in sdram_clk/cpu_clk units. 2 the actual values depend on the setting of the digital lter frequency sampling rate (dffsr) bits in the frequency divider register i2cfdr. therefore, the noted timings in the above table are all relative to quali ed signals. the quali ed scl and sda are delayed signals from what is seen in real time on the i 2 c bus. the quali ed scl, sda signals are delayed by the sdram_clk/cpu_clk clock times dffs times 2 plus 1 sdram_clk/cpu_clk clock. the resulting delay value is added to the value in the table (where this note is referenced). see figure 13. 3 since scl and sda are open-drain type outputs, which the mpc107 can only drive low, the time required for scl or sda to reach a high level depends on external signal capacitance and pull-up resistor values. 4 speci ed at a nominal 50pf load 5d fdr is the decimal divider number indexed by fdr[5:0] value. refer to the i 2 c interface chapter?s serial bit clock frequency divider selections table. fdr[x] refers to the frequency divider register i2cfdr bit x. n is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 16. m is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9. figure 12 through figure 15 show the i 2 c timing diagrams i, ii, iii, and iv respectively. table 14. i 2 c output ac timing specifications at recommended operating conditions (see figure 2 ) with lvdd = 3.3 v 0.3 v num characteristic min max unit notes 1 start condition hold time (fdr[5] == 0) x (d fdr /16) / 2n + (fdr[5] == 1) x (d fdr /16) / 2m ? clks 1,2,5 2 clock low period d fdr / 2 ? clks 1,2,5 3 scl/sda rise time (from 0.5 v to 2.4 v) ? ? ms 3 4 data hold time 8.0 + (16 x 2 fdr[4:2] ) x (5 - 4({fdr[5],fdr[1]} == b?10) - 3({fdr[5],fdr[1]} == b?11) - 2({fdr[5],fdr[1]} == b?00) - 1({fdr[5],fdr[1]} == b?01)) ? clks 1,2,5 5 scl/sda fall time (from 2.4 v to 0.5 v) ?< 5ns4 6 clock high time d fdr / 2 ? clks 1,2,5 7 data setup time (mpc107 as a master only.) (d fdr / 2) - (output data hold time) ? clks 1,5 8 start condition setup time (for repeated start condition only) d fdr + (output start condition hold time) ? clks 1,2,5 9 stop condition setup time 4.0 ? clks 1,2
mpc107 bridge/memory controller hardware speci?ations 23 electrical and thermal characteristics figure 12. i 2 c timing diagram i figure 13. i 2 c timing diagram ii figure 14. i 2 c timing diagram iii figure 15. i 2 c timing diagram iv (qualified signal) scl sda vm vm 6 2 1 4 scl sda vm v l v h 9 8 3 5 input data valid dffsr filter clk 1 sda 7 notes: 1 dffsr lter clock is the sdram_clk/cpu_clk clock times dffsr value. scl/sda realtime vm scl/sda qualified vm delay 1 notes: 1 the delay is the local memory clock times dffsr times 2 plus 1 local memory clock.
24 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics 1.4.3.5 epic serial interrupt mode ac timing speci?ations table 15 provides the epic serial interrupt mode ac timing speci cations for the mpc107. notes: 1 see the mpc107 user?s manual for a description of the epic interrupt control register (eicr) describing s_clk frequency programming. 2 s_rst, s_frame , and s_int shown in figure 16 and figure 17 depict timing relationships to sys_logic_clk and s_clk and do not describe functional relationships between s_rst, s_frame , and s_int. see the mpc107 user?s manual for a complete description of the functional relationships between these signals. 3 the sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic pll; sys_logic_clk is the same as sdram_sync_in when the sdram_sync_out to sdram_sync_in feedback loop is implemented and the dll is locked. see the mpc107 user?s manual for a complete clocking description. figure 15 and figure 16 show the epic serial interrupt mode output and input timing diagrams respectively. figure 16. epic serial interrupt mode output timing diagram table 15. epic serial interrupt mode ac timing specifications at recommended operating conditions (see figure 2 ) with lvdd = 3.3 v 0.3 v num characteristic min max unit notes 1 s_clk frequency 1/14 sdram_sync_in 1/2 sdram_sync_in mhz 1 2 s_clk duty cycle 40 60 % 3 s_clk output valid time ? 6 ns 4 output hold time 0 ? ns 5 s_frame , s_rst output valid time ? 1 sys_logic_clk period + 6 ns 2 6 s_int input setup time to s_clk 1 sys_logic_clk period + 2 ? ns 2 7 s_int inputs invalid (hold time) to s_clk ? 0 ns 2 s_clk s_rst vm vm vm s_frame sys_logic_clk 3 vm vm vm vm 4 3 5 4
mpc107 bridge/memory controller hardware speci?ations 25 electrical and thermal characteristics figure 17. epic serial interrupt mode input timing diagram 1.4.3.6 ieee 1149.1 (jtag) ac timing speci?ations table 16 provides the jtag ac timing speci cations for the mpc107 while in the jtag operating mode. notes: 1 trst is an asynchronous signal. the setup time is for test purposes only. 2 non-test (other than tdi and tms) signal input timing with respect to tck 3 non-test (other than tdo) signal output timing with respect to tck 4 timings are independent of the system clock (pci_sync_in). table 16. jtag ac timing specification (independent of pci_sync_in) at recommended operating conditions (see figure 2 ) with lvdd = 3.3 v 0.3 v num characteristic 4 min max unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ? ns 2 tck clock pulse width measured at 1.5 v 20 ? ns 3 tck rise and fall times 03ns 4 trst_ setup time to tck falling edge 10 ? ns 1 5 trst_ assert time 10 ? ns 6 boundary scan input data setup time 5 ? ns 2 7 boundary scan input data hold time 15 ? ns 2 8 tck to output data valid 030ns3 9 tck to output high impedance 030ns3 10 tms, tdi data setup time 5?ns 11 tms, tdi data hold time 15 ? ns 12 tck to tdo data valid 015ns 13 tck to tdo high impedance 015ns 6 s_clk s_int 7 vm
26 mpc107 bridge/memory controller hardware speci?ations electrical and thermal characteristics figure 18 shows the jtag clock input timing diagram. . figure 18. jtag clock input timing diagram figure 19 shows the jtag trst timing diagram, figure 20 the jtag boundary scan timing diagram, and figure 21 the test access port timing diagram. figure 19. jtag trst timing diagram . figure 20. jtag boundary scan timing diagram tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage 4 5 trst tck 6 7 input data valid 8 9 output data valid tck data inputs data outputs data outputs
mpc107 bridge/memory controller hardware speci?ations 27 package description . figure 21. test access port timing diagram 1.5 package description 1.5.1 package parameters for the mpc107 the mpc107 uses a 33 mm x 33 mm, 503 pin plastic ball grid array (pbga) package. the plastic package parameters are as provided in the following list. package outline: 33 mm x 33 mm interconnects: 503 pitch: 1.27 mm solder attach: 63/37 sn/pb solder balls: 63/37 sn/pb solder ball diameter: 0.60 - 0.90 mm maximum module height: 2.75 mm co-planarity speci cation: 0.20 mm maximum force: 6.0 lbs. total, uniformly distributed over package (5.4 grams/ball) 1.5.2 pin assignments and package dimensions figure 22 shows the top surface, side pro le, and pinout of the mpc107, 503 pbga package. 10 11 input data valid 12 13 output data valid tck tdi, tms tdo tdo
28 mpc107 bridge/memory controller hardware speci?ations package description
mpc107 bridge/memory controller hardware speci?ations 29 package description figure 22. mpc107 package dimensions and pinout assignments
30 mpc107 bridge/memory controller hardware speci?ations package description 1.5.3 pinout listings table 17 provides the pinout listing for the mpc107, 503 pbga package. table 17. mpc107 pinout listing signal name package pin number pin type supply voltage output driver type notes 60x processor interface signals a[0?31] ae22, ae16, aa14, ae17, ad21, ad14, ad20, ab16, ab20, ab15, aa20, ad13, y15, ae12, ad15, ab9, ab14, aa8, ac13, y12, y11, ae15, ae13, aa16, y13, ab8, ad12, ae10, ab13, y9, y8, ad9 i/o bvdd drv_cpu 4 aa ck ac7 output bvdd drv_cpu ? ar tr y y7 i/o bvdd drv_cpu 15 bg0 ae11 output bvdd drv_cpu ? bg1 ad11 output bvdd drv_cpu ? br0 ab17 input bvdd ? ? br1 y14 input bvdd ? 10 ci ad16 i/o bvdd drv_cpu ? dbg0 ac10 output bvdd drv_mem_addr ? dbg1 ad10 output bvdd drv_mem_addr ? dbglb ab10 output bvdd drv_mem_addr ? dh[0?31] p1, r1, p2, t4, t1, t3, r4, p6, u6, v5, v2, t5, u1, r6, w1, v4, w2, u4, t2, v6, w3, w5, y1, y2, y4, y5, aa1, aa2, aa4, ab1, ab3, ab4 i/o bvdd drv_cpu 4 dl[0?31] aa7, w6, ab6, aa6, ab5, ac4, ad3, ab7, ae1, w4, n6, m1, n3, n4, n5, n1, m2, r2, v1, p5, p4, n2, u2, ae4, ae6, ae2, ae3, ae7, ad5, ab2, ac2, ac1 i/o bvdd drv_cpu 4 dp[0?7] ae9, ad6, ad8, ad1, ae8, ad7, ad4, ae5 i/o bvdd drv_cpu 4 gbl ad17 i/o bvdd drv_cpu ? lbclaim y17 input bvdd ? ? t a ae14 i/o bvdd drv_cpu 15 tbst ae21 i/o bvdd drv_cpu ? tea ab11 output bvdd drv_cpu ? ts aa10 i/o bvdd drv_cpu 15 tsiz[0?2] ae19,ad18,ab18 i/o bvdd drv_cpu 4 tt[0?4] ad19,ac19,ab19,aa19,aa18 i/o bvdd drv_cpu 4
mpc107 bridge/memory controller hardware speci?ations 31 package description wt ac16 i/o bvdd drv_cpu ? pci interface signals ad[31?0] n23, n21, m20, m21, m22, m24, m25, l20, l22, k25, k24, k23, k21, j20, j24, j25, h20, f24, e25, f21, e24, e22, d25, a25, b25, a23, b23, b22, c22, c25, d23, d21 i/o ovdd drv_pci 4,11 c/be [3?0] l24, j22, g22, a24, i/o ovdd drv_pci 4,11 devsel g23 i/o ovdd drv_pci 6,11 frame g20 i/o ovdd drv_pci 6,11 gnt [4?0] t24, p22, p21, r22, n20 output ovdd drv_pci 4,11 idsel l25 input ovdd ? ? int a v21 output ovdd drv_pci 6,11,12 ird y h24 i/o ovdd drv_pci 6,11 lock g21 input ovdd ? 6 par g24 i/o ovdd drv_pci 11 perr g25 i/o ovdd drv_pci 6,11,13 req [4?0] w25, v25, u25, t25, t23 input ovdd ? 10 serr f25 i/o ovdd drv_pci 6,11,12 st op h21 i/o ovdd drv_pci 6,11 trd y h25 i/o ovdd drv_pci 6,11 memory interface signals as a4 output gvdd drv_mem_addr ? cas /dqm[0?7] a2, b1, a11, a10, b3, c2, f12, d11 output gvdd drv_mem_addr 4 cke a12 output gvdd drv_mem_addr 1 foe a13 i/o gvdd drv_mem_addr 1,2 mdh[0?31] m6, l4, l6, k2, k4, k5, j4, j6, h4, h5, g3, g5, g6, f5, f1, e1, b14, d15, b15, e16, d16, c16, d18, d17, b17, f18, e19, e20, b19, b20, b21, a22 i/o gvdd drv_mem_data 4 mdl[0?31] m5, l1, l2, k1, k3, j1, j2, h1, h2, h6, g2, g4, f4, g1, f2, e2, f14, f15, a16, f17, b16, a17, a18, a19, b18, e18, d19, f19, a20, c19, d20, a21 i/o gvdd drv_mem_data 3,4 par/ar[0?7] d2, c1, a15, a14, d1, d3, f13, c13 i/o gvdd drv_mem_data 4 table 17. mpc107 pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
32 mpc107 bridge/memory controller hardware speci?ations package description ras/cs [0?7] e6, c4, d5, e4, c10, f11, b10, b11 output gvdd drv_mem_addr 4 rcs0 d10 i/o gvdd drv_mem_addr 1,2 rcs1 b9 output gvdd drv_mem_data ? rcs2 b5 output gvdd drv_mem_addr ? rcs3 d7 output gvdd drv_mem_addr ? sdba0 a9 output gvdd drv_mem_addr 1,2 sdba1 a8 output gvdd drv_mem_addr ? sdcas d4 output gvdd drv_mem_addr 1 sdma [13?0] e10, f9, d9, f8, e8, d8, b8, e7, c7, b7, a7, b6, a6, a5 output gvdd drv_mem_addr 4,5 sdras b4 output gvdd drv_mem_addr 1 we a3 output gvdd drv_mem_addr ? epic control signals int y22 output ovdd drv_cpu 16 irq_0 /s_int u24 input ovdd ? ? irq_1 / s_clk c24 i/o ovdd drv_pci ? irq_2 / s_rst t21 i/o ovdd drv_pci ? irq_3 / s_frame u20 i/o ovdd drv_pci ? irq_4/ l_int v22 i/o ovdd drv_pci ? i 2 c control signals scl ab25 i/o ovdd drv_cpu 8,12 sda ab24 i/o ovdd drv_cpu 8,12 clock signals cko v20 output ovdd drv_pci ? cpuclk[0?2] aa12, aa13, ab12 output bvdd drv_mem_addr 4 osc_in u22 input ovdd ? ? pci_clk [0?4] r25, p24, r24, n24, n25 output ovdd drv_mem_addr 4 pci_sync_in p20 input ovdd ? ? pci_sync_out p25 output ovdd drv_mem_addr ? sdram_clk [0?3] d14, d13, e12, e14 output gvdd drv_mem_addr 4 sdram_sync_in e13 input gvdd ? ? sdram_sync_out d12 output gvdd drv_mem_addr ? table 17. mpc107 pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
mpc107 bridge/memory controller hardware speci?ations 33 package description miscellaneous signals hreset aa23 input ovdd ? ? hreset_cpu ab21 output bvdd drv_cpu 10,12 mcp ae20 output bvdd drv_cpu 10 nmi ac25 input ovdd ? ? qa ck ae18 output bvdd drv_cpu 10 qreq m4 input bvdd ? ? sreset y18 output bvdd drv_cpu 10 test/con?uration signals pll_cfg[0?3] ac22, ad23, ad22, ae23 input ovdd ? 2,4 tck w24 input ovdd ? 7,10 tdi y25 input ovdd ? 7,10 tdo w23 output ovdd drv_pci test aa25 input ovdd ? 7,10 test1 v24 input ovdd ? 8 test 2 d6 input gvdd ? 9 tms y24 input ovdd ? 7,10 trig_in w22 input ovdd ? trig_out w21 output ovdd drv_cpu 10 trst aa24 input ovdd ? 7,10,14 power and ground signals avdd ae24 input ? ? ? gnd aa21, ab22, ac11, ac14, ac17, ac20, ac23, ac3, ac5, ac8, ad24, ae25, c12, c15, c18, c21, c23, c3, c6, c9, e3, f10, f16, f20, f23, f6, g11, g13, g15, g18, g8, h19, h3, h7, j23, k20, k6, l19, l3, l7, m23, n19, n7, p3, r19, r23, r7, t20, t6, u3, v19, v23, v7, w11, w13, w15, w18, w8, y10, y16, y19, y20, y3, y6 input ? ? ? gvdd b2, c5, c8, c11, c14, c17, c20, e5, e9, e11, e15, e17, f3, g7, g9, g12, g14, g17, g19, j3, j5, j7, l5, m3, m7 input ? ? ? lavdd f7 input ? ? ? lvdd d22, f22, h22, k22, n22, t22 input ? ? ? table 17. mpc107 pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
34 mpc107 bridge/memory controller hardware speci?ations pll con?uration notes: 1 this pin has an internal pull-up resistor which is enabled only when the mpc107 is in the reset state. the value of the internal pull-up resistor is not guaranteed, but is suf cient to ensure that a logic '1' is read into con guration bits during reset. 2 this pin is a reset con guration pin. 3 mdl[0] is a reset con guration pin and has an internal pull-up resistor which is enabled only when the mpc107 is in the reset state.the value of the internal pull-up resistor is not guaranteed, but is suf cient to insure that a logic '1' is read into con guration bits during reset. 4 multi-pin signals such as ad[0?31] or dl[0?31] have their physical package pin numbers listed in order corre- sponding to the signal names. ex: ad0 is on pin d21, ad1 is on pin d23,... ad31 is on pin n23. 5 sdma[10?1] are reset con guration pins and have internal pull-up resistors which are enabled only when the mpc107 is in the reset state.the values of the internal pull-up resistors is not guaranteed, but are suf cient to ensure that logic '1's are read into the con guration bits during reset. 6 recommend a weak pull-up resistor (2k ? 10k ohm) be placed on this pci control pin to lvdd. 7v ih and v il for these signals are the same as the pci v ih and v il entries in table 3, ?dc electrical speci ca- tions.? 8 recommend a weak pull-up resistor (2k ? 10k ohm) be placed on this pin to ovdd. 9 recommend a weak pull-up resistor (2k ? 10k ohm) be placed on this pin to gvdd. 10 this pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is suf - cient to prevent unused inputs from oating. 11 this pin is affected by programmable pci_hold_del parameter, see section 1.4.3.3.1, ?pci signal output hold timing.? 12 this pin is an open drain signal. 13 this pin is a sustained tri-state pin as de ned by the pci local bus speci cation. 14 see section 1.7.4, ?connection recommendations,? for additional information on this pin. 15 recommend a weak pull-up resistor (2k ? 10k ohm) be placed on this pin to bvdd. 16 if bvdd = 2.5 v 5%, this microprocessor interface pin needs to be dc voltage level shifted from ovdd (3.3 v 0.3 v) to 2.5 v 5%; this can typically be accomplished with a two resistor voltage divider circuit since int is an output only signal. 1.6 pll con?uration the mpc107?s internal pll is con gured by the pll_cfg[0?3] signals. for a given pci_sync_in (pci bus) frequency, the pll con guration signals set the core/memory/processor pll (vco) frequency of operation for the pci-to-core/memory/processor frequency multiplying, if any. all valid pll con gurations for the mpc107 are shown in table 18. ovdd b24, e21, e23, h23, j19, j21, l21, l23, m19, p19, p23, r21, u19, u21, u23, y23 input ? ? ? bvdd p7, r3, r5, u5, u7, v3, w7, w9, w12, w14, w17, aa3, aa5, aa9, aa11, aa15, aa17, ac6, ac9, ac12, ac15, ac18, ac21, ad2 input ? ? ? vdd k19, w16, t19, g10, g16, k7, t7, w10, w19, w20, y21, aa22, ab23, ac24, ad25 input ? ? ? manufacturing pins ftp[2?3] r20, d24 i/o ovdd drv_pci 4,8 mtp[1?2] b12, b13 i/o gvdd drv_mem_addr 4,9 table 17. mpc107 pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
mpc107 bridge/memory controller hardware speci?ations 35 system design information 1.7 system design information this section provides electrical and thermal design recommendations for successful application of the mpc107. 1.7.1 pll power supply filtering the avdd and lavdd power signals are provided on the mpc107 to provide power to the peripheral logic/memory bus pll and the sdram clock delay-locked loop (dll), respectively. to ensure stability of the internal clocks, the power supplied to the avdd and lavdd input signals should be ltered of any noise in the 500khz to 10mhz resonant frequency range of the plls. a separate circuit similar to the one shown in figure 23 using surface mount capacitors with minimum effective series inductance (esl) is recommended for each of the avdd and lavdd power signal pins. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacitors of equal value are recommended over using multiple values. the circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits. routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important but proportionately less critical for the lavdd pin. table 18. mpc107 microprocessor pll configuration ref pll_cfg[0?] 2 66 mhz part 100 mhz part pci:core ratio vco multiplier pci_sync_in range (mhz) core/mem/cpu range (mhz) pci_sync_in range (mhz) core/mem/cpu range (mhz) 1 0001 25 5 ? 50 4 25 ? 50 25 5 ? 50 4 25 ? 50 1 4 2 0010 12.5 5 ? 25 4 25 ? 50 12.5 5 ? 25 4 25 ? 50 2 4 3 0011 bypass bypass bypass bypass 5 0101 25 5 ? 33 50 ? 66 25 5 ? 50 50 ? 100 2 2 8 1000 16 5 ? 22 50 ? 66 16 5 ? 33 50 ? 100 3 2 9 1001 33 5 ? 44 50 ? 66 33 5 ? 66 50 ? 100 1.5 2 c 1100 20 5 ? 26 50 ? 66 20 5 ? 40 50 ? 100 2.5 2 d 1101 50 5 ? 66 50 ? 66 50 5 ? 66 50 ? 66 1 2 f 1111 clock off 3 not usable clock off 3 not usable off off notes: 1 pll_cfg[0?3] settings not listed (0000, 0100, 0110, 0111, 1010, 1011, and 1110) are reserved. 2 in pll bypass mode, the pci_sync_in input signal clocks the internal core directly, the pll is disabled, and the pci:core mode is set for 1:1 mode operation. the ac timing speci cations given in this document do not apply in pll bypass mode. 3 in clock off mode, no clocking occurs inside the mpc107 regardless of the pci_sync_in input. 4 limited due to maximum memory vco = 200 mhz. 5 limited due to minimum memory vco = 100 mhz. 6 range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
36 mpc107 bridge/memory controller hardware speci?ations system design information figure 23. pll power supply filter circuit 1.7.2 power supply voltage sequencing the notes in table 2 contain cautions illustrated in figure 2 about the sequencing of the external bus voltages and internal voltages of the mpc107. these cautions are necessary for the long term reliability of the part. if they are violated, the electrostatic discharge (esd) protection diodes will be forward biased and excessive current can ow through these diodes. figure 2 shows a typical ramping voltage sequence where the dc power sources (voltage regulators and/or power supplies) are connected as shown in figure 24. the voltage regulator delay shown in figure 2 can be zero if the various dc voltage levels are all applied to the target board at the same time. the ramping voltage sequence shows a scenario in which the vdd/avdd/lavdd power plane is not loaded as much as the ovdd/gvdd power plane and thus vdd/avdd/lavdd ramps at a faster rate than ovdd/gvdd. if the system power supply design does not control the voltage sequencing, the circuit of figure 24 can be added to meet these requirements. the mur420 diodes of figure 24 control the maximum potential difference between the 3.3v bus and internal voltages on power-up and the 1n5820 schottky diodes regulate the maximum potential difference on power-down. figure 24. example voltage sequencing circuits 1.7.3 decoupling recommendations due to the mpc107?s dynamic power management feature, large address and data buses, and high operating frequencies, the mpc107 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc107 system, and the mpc107 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd, ovdd, gvdd, and lvdd pin of the mpc107. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, gvdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should have a value of 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the length of the part. vdd avdd or lavdd 10 ? 2.2 f 2.2 f gnd low esl surface mount capacitors 3.3v mur420 1n5820 mur420 1n5820 2.5v +3.3v +2.5v source +5v source source 5v 3.3v 2.5v
mpc107 bridge/memory controller hardware speci?ations 37 system design information in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd, ovdd, gvdd, bvdd, and lvdd planes to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors: 100?330 f (avx tps tantalum or sanyo oscon). 1.7.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ovdd. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external vdd, ovdd, gvdd, lvdd, bvdd, and gnd pins of the mpc107. the pci_sync_out signal is intended to be routed halfway out to the pci devices and then returned to the pci_sync_in input of the mpc107. the sdram_sync_out signal is intended to be routed halfway out to the sdram devices and then returned to the sdram_sync_in input of the mpc107. the trace length may be used to skew or adjust the timing window as needed. see motorola application note an1794/d for more information on this topic. the trst signal must be asserted during reset to ensure proper initialization and operation of the mpc107. it is recommended that the trst signal be connected to the system hreset signal or pulled down with a 100- to 1k-ohm resistor. 1.7.5 pull-up/pull-down resistor requirements the data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. the processor data bus signals are: dh[0?31], dl[0?31], and dp[0?7]. the memory data bus signals are: mdh[0?31], mdl[0?31], and par/ar[0?7]. if the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (dl[0?31], dp[4?7], mdl[0?31], and par[4?7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. for this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. it is recommended that ar tr y , t a , and ts have weak pull-up resistors (2k ? 10k ohms) connected to bvdd. it is recommended that mtp[1?2] and test2 have weak pull-up resistors (2k ? 10k ohms) connected to gvdd. it is recommended that the following signals be pulled up to ovdd with weak pull-up resistors (2k ? 10k ohms): sda, scl, test1 , and ftp[2?3]. it is recommended that the following pci control signals be pulled up to lvdd with weak pull-up resistors (2k ? 10k ohms): devsel , frame , ird y , lock , perr , serr , st op , t rd y , and int a . the resistor values may need to be adjusted stronger to reduce induced noise on speci c board designs. the following pins have internal pull-up resistors enabled at all times: req [0?4], tck, tdi, tms, trst , br1 , hreset_cpu , mcp , qa ck , sreset , test and trig_out . see table 17, ?mpc107 pinout listing,? for more information.
38 mpc107 bridge/memory controller hardware speci?ations system design information the following pins have internal pull-up resistors enabled only while device is in the reset state: mdl0, foe , rcs0 , sdras , sdcas , cke, sdbao, and sdma[10?1]. see table 17, ?mpc107 pinout listing,? for more information. the following pins are reset con guration pins: mdl0, foe , rcs0 , sdbao, sdma[10?1], and pll_cfg[0?3]. these pins are sampled during reset to con gure the device. any other unused active-low input pins should be tied to a logic one level via weak pull-up resistors (2k ? 10k ohms) to the appropriate power supply listed in figure 17. unused active-high input pins should be tied to gnd via weak pull-down resistors (2k ? 10k ohms). 1.7.6 thermal management information this section provides thermal management information for the plastic ball grid array (pbga) package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design: the heat sink, air ow and thermal interface material. figure 25 depicts the die junction-to-ambient thermal resistance for two typical cases: 1. a heat sink is not attached to the pbga package and there exists high board-level thermal loading of adjacent components. see ?typical upper limit? curve in figure 25. 2. a heat sink is not attached to the pbga package and there exists low board-level thermal loading of adjacent components. see ?typical lower limit? curve in figure 25. figure 25 shows the die junction-to-ambient resistance.
mpc107 bridge/memory controller hardware speci?ations 39 system design information figure 25. die junction-to-ambient thermal resistance 1.7.6.1 internal package conduction resistance for the pbga packaging technology, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case thermal resistance the die junction-to-ball thermal resistance figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. 15 20 25 30 35 40 45 50 0 0.5 1 1.5 2 2.5 typical upper limit typical lower limit die junction-to-ambient thermal resistance ( c/w) airflow velocity (m/s)
40 mpc107 bridge/memory controller hardware speci?ations document revision history figure 26. c4 package with heat sink mounted to a printed-circuit board for this pbga package, heat is dissipated from the component via several concurrent paths. heat is conducted through the silicon and may be removed to the ambient air by convection or radiation. in addition, a second, parallel heat ow path exists by conduction in parallel through the c4 bumps and the epoxy under- ll to the plastic substrate for further convection cooling off the edges. then from the plastic substrate, heat is conducted via the leads/balls to the next-level interconnect (printed-circuit board), whereupon the primary mode of heat transfer is by convection or radiation. 1.8 document revision history table 19 provides a revision history for this hardware speci cation. external resistance external resistance internal resistance (note the internal versus external package resistance.) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
mpc107 bridge/memory controller hardware speci?ations 41 document revision history table 19. document revision history document revision substantive change(s) 0 preliminary release with some tbds in the spec tables. 0.1 removed references to cbga packaging. removed references to bvdd = 2.5v and gvdd = 2.5v until device characterization is complete. corrected ?power supply ramp up? range in figure 2 to show vdd being stable before 100 microsecond pll relock time. modi ed table 4: filled in current values from ibis model. changed ?drv_std? to ?drv_cpu? and changed ?ovdd? to ?bvdd?. added note 10 referencing power consumption on pll supply voltage pins to table 5. updated table 6 pbga package thermal characteristics. corrected dll lock range (dll_extend=1) equation in table 8. modi ed figure 6 reducing t loop propagation delay time from 40 ns to 15 ns. modi ed figure 22 for pbga packaging. updated table 17, the table?s notes, and the corresponding text in section 1.7.5, ?pull-up/pull-down resistor requirements.? modi ed note 5 of table 18 reducing maximum memory vco frequency from 225 mhz to 200 mhz. updated the affected pll_cfg[0-3] entries (0001 and 0010) in the table. revised section 1.7.6, ?thermal management information,? for pbga packaging. 0.2 lowered pci input frequency (pci_sync_in) in table 7 from 25 mhz to 12.5 mhz, see table 18 for speci c details on applicability of lower input frequency. modi ed table 8: completed speci cation numbering. combined pci_sync_in jitter speci cations, 7 and 8, into speci cation 7. added speci cation 9d. updated values for speci cations 7, 9b, and 9c. deleted osc_in jitter (cycle-to-cycle) speci cation. added note 8 to speci cations 1a, 1b, 17, and 18; updated the ?min? part of these speci cations to correspond to the lower pci 12.5 mhz input frequency. added figure 5. replaced input ac timing tbds in table 9 with values. replaced output ac timing tbds for speci cations 12c, 12d, 12e, and 14a in table 10 with values. replaced figure 22 with motorola standard packaging drawing for 503 pin pbga. updated table 18: lowered input frequency on refs 2 and c. ref a changed to reserved. ref 8 is changed to usable for 66 mhz devices.
42 mpc107 bridge/memory controller hardware speci?ations document revision history 0.3 removed references to the suspend (power-saving) mode. section 1.3 technology reference updated from 0.35 m to 0.29 m cmos. updated figure 2 and note 5 to indicate only hreset must transition to a logic 1 in one clock cycle for the device to be in the non-reset state. table 3: changed minimum ?input high voltage,? for ?pci only? from 0.5*ovdd to 0.65*ovdd and added note 6. changed condition on ?input low voltage,? v il , from ?all inputs except osc_in? to ?all inputs except pci_sync_in.? replaced minimum cv ih formula, 0.5*ovdd, with 2.4v value. replaced maximum cv il formula, 0.3*ovdd, with 0.4v value. updated ibis model version from v1.0 to v1.1, changed lvdd references to ovdd in table 4 and notes, changed notes 3 and 4 for the values to be read from the ibis model?s i(min) column, and updated the i ol column values. replaced most tbds in table 5 for with new preliminary power consumption estimates. deleted specs 22 and 23 from table 8; they were dc levels covered in table 3. replaced tbds in table 10 for spec 14b. separated cke output valid timing from speci cation 12b (added 12b1 and 12b2) dependent upon device?s maximum operating frequency; see table 10. replaced tbds in table 15 for specs 3, 5, & 6. modi ed table 17: renamed suspend pin (v24) to test1 and moved it from miscellaneous signals group to test/con guration signals group. added notes about pulling it up to ovdd. renamed rtc pin (d6) to test2 and moved it from memory interface signals group to test/con guration signals group. added notes about pulling it up to gvdd. added note 14 for trst pin. added note 6 for int a pin. also added int a to lvdd pull-up list in section 1.7.5. deleted note 1 from table 18; adjusted remaining note numbers. added paragraph in section 1.7.4 for trst connection. table 19. document revision history (continued) document revision substantive change(s)
mpc107 bridge/memory controller hardware speci?ations 43 ordering information 1.9 ordering information this section provides the part numbering nomenclature for the mpc107. note that the individual part numbers correspond to a maximum core/memory/processor frequency. for available frequencies, contact your local motorola sales of ce. figure 27 provides the motorola part numbering nomenclature for the mpc107. each part number also contains a revision code. this refers to the die mask revision number and is speci ed in the part numbering scheme for identi cation purposes only. 0.4 added bvdd = 2.5 v information to document: table 2, table 3, and table 4. updated table 4 and the associated notes. updated speci c operating conditions at the top of the following tables: table 7 ? table 10, table 12, table 14 ? table 16. replaced figure 22, ?mpc107 package dimensions and pinout assignments,? with a clearer diagram of the 503 pbga package. modi ed table 17: added note 15 for bvdd pull-ups to the following pins: ar tr y , t a , and ts . added note 16 for int signal in bvdd = 2.5 v applications. changed aa ck pin type from i/o to output. changed output driver type from drv_mem_data to drv_mem_addr on the following pins: foe , rcs0 , rcs2 , and rcs3 . deleted rtc signal (d6) from memory interface signals group since it is now test2 in the test/con guration signals group. added pll_cfg[0-3] = 0000 to note 1 of table 18 for reserved settings. added bvdd pull-up information to section 1.7.5, ?pull-up/pull-down resistor requirements.? 0.5 separated v oh and v ol dc specs for cpuclk[0?2] signals at bvdd = 2.5v from the other output pins? dc levels. updated table 8 with correct dll_extend default value. reversed vector ordering for the pci interface signals in table 17: c/be [0?3] changed to c/be [3?0], ad[0?31] changed to ad[31?0], gnt [0?3] changed to gnt [3?0], and req [0?3] changed to req [3?0]. the package pin number orderings were also reversed, meaning that pin functionality did not change. for example, ad0 is still on signal d21, ad1 is still on signal d23, ... ad31 is still on signal n23. this change makes the vectored pci signals in the mpc107 hardware speci cation consistent with the pci local bus speci cation and the mpc107 user manual vector ordering. table 19. document revision history (continued) document revision substantive change(s)
44 mpc107 bridge/memory controller hardware speci?ations ordering information . figure 27. motorola part number key xpc 107 a xx xxx l x product code part identifier package (px = pbga) frequency (66, 100 mhz) (contact local motorola sales office) revision level part modifier application modifier (l = standard spec., 0 to 105 ? c t j )
mpc107 bridge/memory controller hardware speci?ations 45 ordering information
46 mpc107 bridge/memory controller hardware speci?ations ordering information
mpc107 bridge/memory controller hardware speci?ations 47 ordering information
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. ther e are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual perfor mance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical ex perts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or autho rized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, o r for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer pu rchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employe es, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that moto rola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu. minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong . 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments : fax (512) 933-2625, attn: risc applications engineering world wide web addresses : http://www.motorola.com/powerpc http://www.motorola.com/netcomm mpc107ec/d digitaldna is a trademark of motorola, inc. the powerpc name, the powerpc logotype, and powerpc 603e are trademarks of international business machines corporation used by motorola under license from international business machines corporation.

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